Recently, semiconductor memories represented by a DRAM (Dynamic Random Access Memory) increasingly grow in storage density, and operations thereof at high speed have been demanded. An increase in storage density is mainly achieved by downsizing of memory cells and large-sizing of a chip size. However, there are problems in that the downsizing of the memory cell has a certain physical limitation, and the large-sizing of the chip size leads to lowering of yield and prevents its high speed operations.
As a method of fundamentally solving this problem, there a have been proposed methods where a core unit in which memory cells are formed and an interface unit in which peripheral circuits for the memory cells are formed are separated into different chips (see Japanese Patent Application Laid-open Nos. 2004-327474, 2005-191172, and 2006-13337). According to these methods, a plurality of pieces of core chips can be assigned to one interface chip, and thus, it becomes possible to remarkably reduce a chip size per chip. Accordingly, these methods are expected to achieve a much larger density while maintaining a high yield.
Besides, when the core unit and the interface unit are separated into different chips, a core chip can be manufactured by a memory process and an interface chip can be manufactured by a logic process. Generally, transistors manufactured by the logic process can operate at higher speed, as compared to transistors manufactured by the memory process. Thus, when the interface chip is manufactured by the logic process, it becomes possible to operate a circuit of the interface chip unit at higher speed as compared to a conventional case. As a result, it becomes possible to achieve higher speed operations of the semiconductor memory. Further, it also becomes possible to decrease an operation voltage of the interface chip to about 1 V, and thus, a reduction in power consumption can also be implemented.
Further, as described in Japanese Patent Application Laid-open Nos. 2004-327474, 2005-191172, and 2006-13337, when a plurality of these semiconductor chips are stereoscopically stacked, it becomes possible to suppress an increase in packaging area on a printed circuit board.
In the stacked semiconductor device, the core chip and the interface chip are connected by through electrodes. The through electrode is provided to penetrate through a semiconductor substrate that configures the core chip and the interface chip, and is very small in parasitic capacitance and parasitic inductance, as compared to a bonding wire, a TAB tape, or the like. Thus, the through electrode does not lead to an increase in area in a plane direction like signals between chips, so that it greatly contributes to downsizing of the entire stacked semiconductor device.
Such a chip stacking technique is considered to be applied not only to the semiconductor memory such as the DRAM but also to an overall semiconductor device.
FIGS. 11A to 11C are process charts for explaining a method of manufacturing a stacked semiconductor device.
As shown in FIG. 11A, a plurality of through electrodes 13 having a predetermined depth are firstly formed on a main surface 11 of a semiconductor substrate 10 in which an internal circuit (not shown) formed of a transistor or the like is formed. At this stage, the through electrodes 13 do not penetrate through the semiconductor substrate 10, and accordingly, does not appear on a rear surface 12 of the semiconductor substrate 10.
As shown in FIG. 11B, the rear surface 12 of the semiconductor substrate 10 is then polished until the through electrodes 13 are exposed. As a result, the through electrodes 13 appear on the both surfaces of the semiconductor substrate 10. The polishing of the semiconductor substrate 10 can be performed by each chip, or can be performed in a wafer state. Thus, a stacked semiconductor device 20 is completed. Thereafter, as shown in FIG. 11C, when a plurality of stacked semiconductor devices 20 are placed on top of each other via an interchip interconnect 14, a stacking module is formed. It then becomes possible to be packaged on a mounting substrate 30 such as the interface chip or the like.
FIG. 12 is a partial schematic cross-section of the semiconductor substrate 10 shown in FIG. 11A, before being polished.
As shown in FIG. 12, between the through electrode 13 and the semiconductor substrate 10, an insulating film 15 for insulating the both components is arranged. However, due to certain reasons, an insulation breakdown can sometimes occur in the insulating film 15, and in this case, the through electrode 13 and the semiconductor substrate 10 are in a short-circuited state (see a defective portion A). Further, above the through electrode 13, wirings 16a and 16b or the like are arranged. These components are connected by contacts 17a and 17b. However, when displacement occurs to the contact 17a for connecting the wiring 16a and the through electrode 13, the through electrode 13 and the semiconductor substrate 10 are in a short-circuited state (see a defective portion B).
Most of such short-circuit defects lead to a current defect and an operation defect. Thus, these defects are found in a selective test performed in a wafer state, and treated as a defective chip. However, there are various states of the defective portions, and thus, not all the short-circuit defects can be found in the selective test performed in a wafer state. That is, in a complete short-circuited state, a relatively large amount of current passes between the through electrode 13 and the semiconductor substrate 10, and thus, the short-circuit defects are easily found as the current defect or the operation defect in the selective test. However, as far as a defect in a slight short-circuited state does not cause the current defect or the operation defect, the chip may pass the selective test. Although such a slight short-circuit defect poses no problem as far as a single chip is concerned, there is a possibility that the operation defect is caused after a plurality of chips are stacked. Thus, there is a case that such a defect can be a reason for deteriorating a product yield after a stacking process.